Vision & Sensors

Camera Link Steps Up to New Challenges

December 2, 2010
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New Camera Link HS standard is poised to be the highest bandwidth

The serdes components chosen are available at low cost from multiple vendors as discrete chipsets or as IP code that may be embedded into popular field-programmable gate arrays (FPGA) from vendors such as Xilinx or Altera. Source: Xilnix


Offering high bandwidth, real time signaling and control, and deterministic data transfer, Camera Link has become one of the leading digital standards dedicated to the industrial vision market.

Until now, Camera Link has offered the highest performance of the available standards and generally exceeded market needs, but things are rapidly changing as we move toward the future.

Today, new complementary metal-oxide semiconductor (CMOS) sensors are continuously pushing the resolution and speed boundaries upwards. With products on the market capable of 2-megapixel resolution and 10-bit output at 300 frames per second, the resultant data rates can exceed 5.7 gigabytes per second (Gb/s) or 720 megabytes per second (Mb/s).
 
In addition, it does not stop there. Higher speed devices such as the 3-megapixel 485 frames per second LUPA-3000 sensor introduced by Cypress Semiconductor and a 16K line scan imager developed by Awaiba are capable of data throughput rates above 10 Gb/s. 
 
Even Kodak’s new charge-coupled device-based quad-tap 5.5-micron series imagers can exceed 1.2 Gb/s. While not exceedingly high bandwidth, the quad-tap output results in data widths of 32-bits/clock (8-bit/tap) or 40 bits/clock (10-bit/tap). While that falls within the limits of the current Camera Link standard, it only does so if a more complex “medium” configuration with a second cable is utilized.
 
For these reasons, the Automated Imaging Association’s (AIA) Camera Link committee has realized that increases in bandwidth, as well as the simplification of the physical layer are needed going forward.
While Camera Link today can support data rates up to 6.1 Gb/s, this requires the use of two cables, potentially making such products more complicated to manage in real-world environments. The single-cable base configuration of Camera Link can handle up to 2 Gb/s, but many products are already pushing past this rate and will soon require a more complicated two-cable solution.
 
To address these issues and add functionality, while maintaining the Camera Link concept and benefits, the committee has begun work on a new standard called Camera Link HS. Camera Link HS maintains the Camera Link concept of leveraging existing technology pieces, driven by their own larger market demand and lifecycles, to build a standard specific to the needs of the imaging market.
 
To achieve continuous, deterministic data transfers up to 48 Gb/s and maintain low latency signaling and communications, Camera Link HS will borrow from existing standards for 8-bit/10-bit encoding, off-the-shelf serializer/deserializer (serdes) chips for the physical layer (PHY), and K-codes for prioritization of data and commands.
 
Additionally, Camera Link HS will use the European Machine Vision Association (EMVA) GenICam standard for communication protocol and to achieve plug-and-play operation with the host system.
The serdes components chosen are available at low cost from multiple vendors as discrete chipsets or as IP code that may be embedded into popular field-programmable gate arrays (FPGA) from vendors such as Xilinx or Altera.
 
Like Camera Link, Camera Link HS will provide a complete vision interface, including data transfer, low latency camera control signals, timing signals from the camera to the host and bidirectional serial communications. Camera control signaling has been expanded to be bidirectional and include provisions for trigger, strobe and GPIO functions.
 
Interconnection between Camera Link HS components is possible with off-the-shelf copper and fiber optic solutions. The original proposal was to use CX4 from the Inifiniband standard, which can achieve distances up to 15 meters. However, parallel coaxial solutions, capable of up to 80 meters on RG59, are now being investigated.
 
The use of 8-bit/10-bit encoding allows direct streaming into several fiber optics modules to achieve longer distances or extreme electromagnetic compatibility (EMC) immunity. Because the PHY is configured as a standalone piece of the interface and separate from the IP core, it is possible to consider and easily port Camera Link HS onto many available physical mediums.



Camera Link’s base configuration supports 24-bit video plus real-time signaling over a single cable for up to 2 Gb/s data transfer at 85 MHz. Higher rates require a “medium” or “full” two-cable configuration supporting up to a maximum of 6.8 Gb/s at 85 MHz. Source: JAI Inc.

KEY COMPONENT

Key to the Camera Link HS concept is the IP core. The IP core is built around three basic components: a packet engine to package and transfer camera and signaling data; a K-code manager which controls and prioritizes data flow and contains provisions for an external trigger, strobe, general-purpose input/output (GPIO) and housekeeping functions; and an error handler.

The use of K-code technology allows signals dependant on low latency, such as trigger and GPIO commands, to be prioritized at a high level and packaged into smaller packets, which are then sent immediately between larger data packets. Though the signaling packets are sent at a higher priority than data packets, the system is robust and has bandwidth enough to maintain the data transfer in low latency synchronization with the source device (camera).
 
Another unique feature that will be added by Camera Link HS is data forwarding. The video data is packaged in such a way that it may easily be separated into slices. This combined with a 300 Mb/s command channel make it possible for the image to be easily and efficiently shared among multiple parallel processors.

Since one of the fundamental purposes of Camera Link HS is to connect cameras producing video data up to 48 Gb/s, and because in the machine vision market it is presumable that the operator needs to be able to do real-time processing on each image, data forwarding to allow parallel processing is fundamental to many potential applications and is a key differentiator from other vision protocols.
 
By maintaining the original Camera Link concepts, preserving its place as the highest bandwidth standard and adding additional features, Camera Link HS is poised to be the next standard in vision and should have serviceability greater than 10 to 20 years. Camera Link HS will remain as the highest performance standard with the lowest cost of implementation and maximum flexibility, while still offering a complete interface for image transfer, signaling, control and communications.
Today, a sub-committee to the AIA Camera Link Committee, with participants from multiple camera, frame grabber and cable companies, meets regularly to work on the Camera Link HS standard. Early prototypes have already been displayed at various industry events. A draft specification is expected to be released in the first quarter of 2011, with finalization and commercial products to follow within approximately one year. V&S


TECH TIPS

  • Interconnection between Camera Link HS components is possible with off-the-shelf copper and fiber optic solutions.

  • Key to the Camera Link HS concept is the IP core.

  • Data forwarding to allow parallel processing is fundamental to many potential applications and is a key differentiator from other vision protocols.

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