SRC and an environmental research center employ real-time monitoring to slash water and energy usage for semiconductor manufacturing. Thirty percent reduction in wafer surface cleaning requirements can benefit manufacturing sustainability for both 300-millimeter and 450-millimeter processes.

Researchers sponsored by Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, today announced that they have developed new sensor and metrology technology that provides a significant reduction of water-and related energy-usage in the manufacturing of semiconductors.

Introducing the most significant metrology improvements for the rinse and cleaning of wafers in more than a decade, the SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing team at the University of Arizona (UA) has created a sensor-based approach that delivers a 30 percent savings in water and energy for ultra-clean production.

To overcome the dilemma of surface preparation as one of the largest users of water, the ERC team provides a real-time monitoring solution that is unprecedented as an approach to significantly curb excessive use of resources. Applicable to current cleaning processes for 300 millimeter (mm) silicon wafers, the gain is expected to be especially beneficial to chipmakers as they enter into fabrication with much larger, next-generation 450mm surface areas.

With an objective to sustain manufacturing feasibility and continue Moore’s Law, the collective chip industry’s International Technology Roadmap for Semiconductors has an agreed goal of lowering resource utilization for both immediate and next-generation fabrication processes. Among the environmental challenges that the industry will face in the move to 450mm is how to hold down costs and materials needed for cleaning and preparing a surface that’s more than twice the size of current state-of-art wafers.

“This technology can help to clear a big hurdle for semiconductor equipment and manufacturing companies, and we plan to commercialize it since there is no comparable alternative,” said Farhang Shadman, lead researcher and the ERC director at UA for the SRC-funded research. “With this unprecedented sensor application, we’re blunting the anticipated escalation of demand for more resources during surface preparation of the larger and more complex wafers.”

Surface preparation typically consists of three steps: 1) cleaning with specific chemicals suitable for the surface and materials that are being processed, 2) rinsing to remove the chemicals and by-products from the cleaning process, and 3) drying to remove water from the surface.

The current practice is recipe-based and not controlled with real-time, in-line monitoring of the progress of the process steps. Since there is no in-line, real-time metrology, there is no real-time feedback nor control. The processes are typically conducted with a very large cushion of safety to overcome lack of regulation. This sizeable safety factor creates unnecessary waste of chemicals, water and energy-much more than what the processes actually need when controlled properly.

“The challenge is how to balance a minimal application of precious resources with the grave risk of allowing contamination to occur, which can kill huge investments made elsewhere in the fabrication process,” said Dr. Steve Hillenius, executive vice president for SRC. “The ERC solution allows SRC members and other semiconductor businesses to advance both the environmental and technological progress dictated by the industry roadmap.”

In addition to semiconductor equipment and manufacturing companies, other industries that use ultra-clean for planar or patterned surfaces and small structures stand to benefit from this progress in metrology. For example, optics, optoelectronics, and flat panel display are expected to show great interest in the tightly regulated process. As this new sensor technology moves quickly toward commercialization, development is underway for its integration into surface-preparation tools.

For more information about the research, please visit Contributors for the joint effort include K. Dhane, J. Han, J. Yan, O. Mahdavi, D. Zamani, B. Vermeire and F. Shadman.